Description
Job Requirements
- Strong Debug, UVM, System Verilog
- Understanding Specs and Standards and developing relevant test plans
- Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved.
- Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening
Work Experience
- Strong Debug, UVM, System Verilog
- Understanding Specs and Standards and developing relevant test plans
- Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved.
- Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening